DEVICE SUPPORT LISTS JTAG BSDL FILES DFT GUIDELINES APPLICATION NOTES F.A.Q.s	DEVICE SUPPORT Download device support lists for our programmer range. These include an overview of JTAG compatible devices and Altera FPGA and EPCS parts supported by our AP-Selector software on the AP-114. Programmer Software Notes AP-1164 APPC Last updated 4 May 2010 AP-114 AP-SELECTOR JTAG Compatible support Please note that this list is indicitive only, and that ANY JTAG-compatible device is supported by the AP-114, providing you are able to supply a file in a valid JAM/STAPL, SVF or JBC format Last updated 6 May 2010 AVR-isp Atmel AVR     Last updated 6 May 2010 APPC Non-JTAG device Support      Last updated 4 May 2010
	JTAG Joint Test Action Group (JTAG) is the common name for the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. It was initially devised for testing printed circuit boards using boundary scan and is still widely used for this application. Whilst the standard has existed since the early 1990's, its potential as a programming and test tool is only just beginning to be fully appreciated. With the semiconductor industry moving increasingly towards small form factor, high pin-count devices, JTAG provides a reliable method of programming compliant devices In-Circuit, and then allows testing of the circuit board - not only of the JTAG scan-chain itself, but of any components connected to the JTAG chain, including open and short circuits on a board Guide to JTAG [more] In-System Programming (ISP) In-system programming is the ability of some microcontrollers, programmable logic and memory devicesto be programmed while installed in a complete system, rather than requiring the chip to be programmed prior to fitting       [more] Testing non-JTAG devices It is possible to test non-JTAG devices on-board via a JTAG compliant device.   [more] Compatible JTAG files There are a number of diffferent file formats that are compatible with the 1149.1 JTAG standard. AP-SELECTOR supports all popular formats, which enable universal programming and configuration support for JTAG devices STAPL (Standard Test and Programming Language) Jam-Byte Code (JBC) Serial Vector Format (SVF) [more]
	BSDL FILES Boundary Scan Description Language (BSDL) is a subset of VHDL that is used to describe how JTAG is implemented in a particular device. For a device to be JTAG compliant, it must have an associated BSDL file. Our Boundary Scan test software, AP-SCAN will use the information contained in a BSDL file to work out how to access a device in the JTAG chain. These files are available for download from the device manufacturers' websites. [more]
	DFT GUIDELINES Using our DFT (Design-for Testability) Guidelines, it is possible to ensure that as much of your circuit as possible is testable with JTAG, even the non-JTAG components [more]
	APPLICATION NOTES JTAG/Jennic Training Platform - demonstration board [more] LabVIEW Integration [more] COM-object usage - APPC Programming Center [more] COM-object usage - AP-Scan Boundary Scan Software [more] Jennic Debugger - JN5148 ZigBee Wireless Microcontroller [more]
	FREQUENTLY ASKED QUESTIONS AP-SCAN Boundary Scan Software [more]