Boundary Scan
Description Language (BSDL) is a subset of VHDL that is used to
describe how JTAG is implemented in a particular device. For a device
to be JTAG compliant, it must have an associated BSDL file.
These files
are available for download from the device manufacturers' websites
(see below).
Our Boundary
Scan test software, Infinity SCAN, will use the information contained in a
BSDL file to work out how to access a device in the JTAG chain.
BSDL files contain the following elements:
Entity Description
Statements naming the device or a section of its functionality
Generic Parameter
A value such as a package type. The value may come from outside the
current entity
Logical
Port Description
Describes the nature of the pins on the device (input, output,
bidirectional, linkage)
Use Statements
References external definitions (such as IEEE 1149.1).
Package Pin Mapping(s)
Maps logical signals in the device to physical pins.
Scan Port Identification
Defines the pins used on the device to access the JTAG capabilities
(TDI, TDO, etc - the Test Access Port).
Test Access
Port (TAP) Description
This parameter provides additional information on the boundary-scan
or JTAG logic for the device. The data includes the instruction
register length, instruction opcodes, device IDCODE, etc.
Boundary
Register Description
List of the boundary scan cells and their functionality. Each pin on
a device may have up to 3 cells, with each cell consisting of a
register and a latch
Download BSDL files for your JTAG components:
|
Actel
Agilent
Technolgies
Altera
AMD
Analog
Devices
Atmel
Cirrus
Logic
Cypress
Fairchild
Freescale
(formally Motorola)
Fujitsu
GSI
Technology
IBM |
IDT
Infineon
Intel
Intersil
ISSI
Lattice
Semiconductors
LSIMaxim
Micron
Mindspeed
Mosel
Vitelic
Music
Semiconductors
National
Semiconductor
NEC |
OKI
Philips
Phytec
PMC
Sierra
QuickLogic
Renesas
Samsung
Silicon
Laboratories
STMicroelectronics
Texas
Instruments
Toshiba
Xilinx
Zarlink |
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